De1 Pin Assignments.Csv Download Movies

The Cyclone II EP2C20F484C7 FPGA on the DE1 logic kit is connected to four seven segment displays, (Hex_0, Hex_1, Hex_2, and Hex_3), ten slide switches (Switch_0 through Switch_9), four push buttons (Key_0 through Key_3), ten red LEDs (Red_LED_0 through Red_LED_9), and eight green LEDs (Green_LED_0 through Green_LED_7).

The slide switches produce logic “1” when pushed away from the edge of the board, and the push buttons produce logic “0” when pressed. The segments of the seven segment displays light up when connected to logic “0,” and the LEDs light up when connected to logic “1”. The following table shows which FPGA pin numbers are connected to these devices.

The segments of a seven-segment display are normally named A–G, starting at the top, going clockwise, and ending with the center segment. The array names in the table refer to the segments using subscript values 0–6 in the same order.

To make the process of pin assignment easier, the following table is in alphabetical order, which should match the order of the pins listed by the Quartus Pin Assignment Editor, provided you name your pins and pin groups alphabetically: Clock…, Green…, Hex_0…, Hex_1…, Hex_2…, Hex_3…, Key…, Red…, and Switch… in that order.

ConnectionPin Location
27 MHz ClockPIN_D12 and PIN_E12
50 MHz ClockPIN_L1
24 MHz ClockPIN_A12 and PIN_B12
Green LEDs
Seven-segment Displays
Hex_0, Decimal PointNo Connection
Hex_1, Decimal PointNo Connection
Hex_2, Decimal PointNo Connection
Hex_3, Decimal PointNo Connection
Push Buttons
Red LEDs
Slide Switches

Presentation on theme: "Teaching Digital Logic courses with Altera Technology"— Presentation transcript:

1 Teaching Digital Logic courses with Altera Technology
Tutorial #1

2 Learn how to use Quartus:
OutlineLearn how to use Quartus:Creating projects in Quartus IITargeting a project for a DE1-SoC BoardDownloading a circuit onto a DE1-SoC boardCompiling and debuggingOverview of tutorials and lab exercises for teaching digital logic using QuartusProvide context; learn how to use quartus, then talk about teaching materials we have that use quartus

3 Exercise 1: A Simple Quartus Project
Open a Quartus ProjectCompile a simple circuit10-bit shift registerRegister input: switchShift on key pressRegister values displayed on LEDsProgram FPGA with circuitExamine behavior on the board

4 Step 1: Start Quartus II Project Navigator Status Window
Message Window

5 Step 2: Create a New Project
Click File MenuSelect New Project WizardThis will open a new window where project information can be specified

6 Project Name and Directory

7 Add Source Files to Project

8 Select the FPGA device on the board
Specify FPGA DeviceSelect the FPGA device on the boardCyclone V Family – 5CSEMA5F31C6

9 Specify Tools, in addition to Quartus II, that you will use
Additional EDA ToolsSpecify Tools, in addition to Quartus II, that you will useThese are unnecessary for small student designsLeave all entries as <None>Press Next

10 New Project Summary

11 Simple Project 10-bit Shift Register … LED[9] LED[2] LED[1] LED[0]
SW[0]KEY[0]KEY[1]InputReset_NClock10-bit Shift Register…LED[9]LED[2]LED[1]LED[0]

12 Step 3: Open Source FileCan open it up by using project navigator. Briefly describe the circuit (SW, key, ledrs connected), some description of the shift register.

13 Step 4: Assign Pins to connect switches/lights to inputs and outputs of your circuit
Click Assignments, then Import Assignments…Import fileDE1_SoC.qsfImports locations for predefined port names, such as SW, LED, KEY, and othersCan be done manually tooOpen the file (qsf) and show them LEDR -> mapping to PIN

14 Step 5: Compile Design Placement Timing & Power Synthesis & Routing
Verilog,VHDLSynthesisPlacement& RoutingTiming & PowerAnalysisAssemblerReportBriefly explain

15 Step 6: Examine Compilation Report
More on pin assignments – look at the board

16 Step 7: Program the Board
Blue LEDs will flash

17 Step 8: See your design work on the board
Press the KEY[0] to clock the circuitSW[0] is the input to the shift registerReset the shift register using KEY[1]Red LEDs10-bit Shift RegisterInputReset_NClockSW[0]KEY[1]KEY[0]Replicate the picture from before

18 Please read the instructions at Use provided source code “simple.v”
Hands-On SessionPlease read the instructions at“/Digital Logic/simple/simple_instructions.pdf”Use provided source code “simple.v”We will be walking around to help with any issues (such as USB programming)

19 Next ExampleOpen the Digital Logic folderGo into stopper subfolderOpen the stopper.qpf Quartus II project

20 Shift the contents of a register once every ~0.1 second
Exercise 2: StopperShift the contents of a register once every ~0.1 secondThe circuit is clocked using a 50MHz clockPress KEY[0] to start or stop the shift registerFSM examines if the key was pressedPurpose:Look at FSM implementation in Quartus IIFinite State Machine Viewer

21 Circuit Diagram KEY[0] FSM Clock Divider 10-bit Shift Register Clock
Fast Slow10-bit Shift RegisterenableClockClockPicture… 50Mhz counter, counter, SR, FSM. Pressing the key will toggle the FSM state, start/stop the shifting. FSM is used as a puslse generator which gives 1 cycle pulse when key is pressed. ADD toggle flip flop TO THIS PIC (THE REG THAT IS TOGGLED BY FSM)Red LEDs

22 Step 1: Open Stopper Project

23 Step 2: Compile and Program
Compile the designProgram the design onto the boardHow does it work?Press KEY[0] to start/stop the circuitPress KEY[1] to reset the circuit

24 Step 3: Examine the FSM Source Code
Add a state diagram before this slide. Briefly describe FSM (3 states, this part gives state transitions, this part gives etc,).

25 Step 4: FSM Viewer Open the FSM Viewer Click Tools
Expand Netlist ViewersClick State Machine Viewer

26 Examine State MachineWhen FSM written properly in accepted way, quartus will detect it and display it here.

27 Please read the instructions at Use provided project “stopper.qpf”
Hands-On SessionPlease read the instructions at“/Digital Logic/stopper/stopper_instructions.pdf”Use provided project “stopper.qpf”

28 Next Example: Signal Tap II Logic Analyzer
Go into signaltap subfolderOpen the signaltap.qpf Quartus II projectCompile the project, and program the boardCreate a virtual logic analyzer in the fabric of the FPGA that can connect to any nodes in the circuit (not just I/O), store the results and display them.

29 SignalTap II Embedded Logic Analyzer
A logic analyzer IP coreInstantiate in your Verilog codeConnects to the board on which a design is runningCollects data when a trigger event occursDisplays data on your computer

30 SignalTap II Operation
USB-BlastercableFPGASignalTap ModuleKEY[0]FSMKEY[1]10-bit Shift RegisterenableClockDoes this thru USB blaster (need no extra tools! No need for expensive logic analyzer).ClockRed LEDs

31 Setup SignalTap II Specify cable connection Specify Clock signal
Specify signalsto display

32 For changes to take effect recompile project
Once recompiled, download it to the boardNote: The circuit will be larger than beforeMemory is used to store captured data

33 Setup Event Trigger Click here to begin capture
UPDATE screenshot (DE-SoC vs SoCKit)! Sample depth! When the event occurs, it will store the data for x cycles (ex 128 shown) and display the data. Some cycles worth of data before the event as well.

34 Trigger the event and Analyze the results
Use same circuit as previous example (if use previous, LEDS might not shift. Would have to get rid from analyzer).

35 Please read the instructions at Use provided project “signaltap.qpf”
Hands-On SessionPlease read the instructions at“/Digital Logic/signaltap/signaltap_instructions.pdf”Use provided project “signaltap.qpf”

36 Summary of Tutorial #1 Learned how to Use Quartus II CAD Software
Compile projects in Quartus IITarget design onto DE1-SoCView results of compilationUse SignalTap IIHeres what we learned, let me talk about materials you can use for your students

37 Tutorials Tutorials Getting Started with Altera’s DE-series Lab Boards
Introduction to Quartus IITutorialsGetting Started with Altera’s DE-series Lab BoardsIntroduction to Quartus IIWith Verilog, or VHDL, or SchematicUsing library modules (LPMs)With Verilog or VHDLQuartus II SimulationUsing ModelSim for AlteraUsing TimeQuest Timing AnalyzerSignal Tap II Logic AnalyzerOpen up the tutorial, show that it is a complete doc, written like textbook.373737

38 Digital Logic Lab Exercises
Verilog and VHDL versionsFrom basic logic gates to simple processors:Switches, Lights, and MultiplexersNumbers and DisplaysLatches, Flip-flops, and RegistersCountersReal-time Clock and TimersAdders, Subtractors, and MultipliersFinite State MachinesMemory BlocksA Simple ProcessorAn Enhanced ProcessorAlgorithms in HardwareDigital Signal ProcessingSample curriculumSet of lab exercises we developed for the digital logic start assuming no knowledge. Simple circuits connecting lights, multiplexers. Later exercises become more advanced and use the simpler circuits from previous exercises, and build more advanced circuits. Fits very well with the way that you would teach a course like this are advanced, not for beginner courses.383838

39 Lab Exercises and Solutions
Exercises and complete solutions on U.P. web sitePassword protected (Professors/Lecturers)Includes all Quartus II projectsIncludes all figures and source text (allows Instructors to add their own material)RETAKE pic to include exercise 11,12. Also remove part5.Verilog from document_files. We ALSO provide the latex files for the lab writeups so that you can modify them for your course. Mention that we provide verilog AND VHDL solutions and writeups.393939

40 Organization of Lab Exercises
Simple HDL assignments that directly correspond to Boolean equationsNo magic!Block-based design in which each block of code corresponds to a well-defined subcircuitHDL code is not a “program”!!Smaller circuits are built first, and then used to construct larger onesGood design practiceWe though carefully about how to present the exercises to ensure they learn properly. Ex. In first few examples, students cant use advanced verilog features. Can only use boolean eequations. Want students to know they are designing circuits. Type of verilog code we show clearly corresponds to a circuit; easy to see that each part of the code corresponds to circuit. Smaller -> larger, good design practice used in industry.404040

41 Lab 1: Switches and Lights
/* connect switches to lights through FPGA */assign light_0 = switch_0;assign light_1 = switch_1;. . ./* build a 2-to-1 multiplexer */Part 1SuggestedsolutionPart 2Go through a few slides to give a feeling for the flow of the learning. Lab 1: this is the beginning point. Part 1 assumes students don’t know anything. Open the solution .v. Move on to part 2 the simplest circuit that you can use to build a circuit.414141

42 … Lab 1 assign m = (~s & x) | (s & y); …
Make 8 copies, connect to 8 red LEDsPart 2SuggestedsolutionBuild a more complex multiplexer:3-bit wide 5-to-1 multiplexerPart 3SuggestedsolutionNotice that we are not using IF statements. Use boolean equations to make sure students know what they are doing.424242

43 … Lab 1 Suggested solution Part 4
7 seg decoder that can display 4 different letters434343

44 … Lab 1 Make 5 copies of this Suggested solution Part 5 Part 5
Putting together the circuits from the previous parts, you ave the ability to display character patterns. Using only simple 2-1 muxes and a 7-seg decoder, we can make an interesting circuit that can rotate a word across the display. Emphasize hierarchichal fashion small -> largerSuggestedsolution444444

45 Latches and Flip-flops
Lab 2 and Lab 3Numbers and DisplaysDisplay binary numbers on 7-segment displaysConvert binary to Binary Coded DecimalSimple ripple-carry additionLatches and Flip-flopsImplement RS latch in an FPGAImplement D latchMaster-slave flip-flop as latchesD registers as Verilog code Clock or negedge Resetn) Q <= R;As move forward, deal with more complex circuits, display numbers, adders. Start using sequential circuit elements.4545

46 Lab 4: Counters assign Enable_0 = SW[1];
SuggestedsolutionPart 1assign Enable_0 = SW[1];ToggleFF (Enable_0, Clock, Clear, Count_0);assign Enable_1 = Count_0 & Enable_0;ToggleFF (Enable_1, Clock, Clear, Count_1);. . .464646

47 . . . … Lab 4 /* use some more advanced Verilog */ …
Count <= Count + 1;Part 2Suggestedsolution. . .CountPart 5Reusing the circuit from lab 1 that scrolled HELLO, but instead connect a counter instead of SW to do this. Another example of reusing circuits.CountSuggestedsolution474747

48 To Students: Write “Obvious” HDL Code
Comparatorassign T = A + B;(T)if (T > 9)beginZ = 6; C = 1;endelseZ = 0; C = 0;assign S = T + Z;AdderMultiplexer that selectsconstantsEven when we allow students to use more advanced features of verilog, still make sure each line clearly corresponds to a piece of the circuit. A nice feature of Quartus is to use the RTL viewer to display that the circuit described is actually what you are expecting.Adder484848

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